This design example provides a simple hardware and software examples that showcases the use of modular SGDMA (mSGDMA) to transfer memory content from one location to another. Overview
Intel® Quartus® Prime Pro v18.1 or later
Intel® Arria® 10 SoC Development Kit (if hardware testing is required)
Host PC with JTAG connection to the on-board USB Blaster II
Details on Hardware and Software design
The host PC serves to provide the .elf file to the Nios® II processor via JTAG and resets it. Once the processor starts to run, it firstly populate an initial memory location in the FPGA on-chip RAM with a known pattern. Then, it creates and write descriptors into the mSGDMA to move the content to another location in the FPGA on-chip RAM. Once the mSGDMA transfer is complete, it checks and ensure that the the content at the new memory location is similar to the original values. User can check the status of the software via the nios2-terminal that is linked through JTAG to the host PC.
Using cable "USB-BlasterII on xxx [USB-1]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 80KB in 0.1s Verified OK Starting processor at address 0x00000238 nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-BlasterII on xxx [USB-1]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
Attempting to open MSGDMA... Memory copy successful. Session will now close.
nios2-terminal: exiting due to ^D on remote bash-4.1$