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I cannot see the model name physically on the chip, as it is covered by the fan. The OPN# on the sticker of the box is DK-DEV-1SGX-L-0ES.
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Hi Xiaowei Wang,
The ordering code provided by you,is of Stratix 10 GX FPGA Development Kit L-Tile Edition (ES Version) so if you refer the Table 1. from below link for Stratix 10 GX FPGA L-Tile then target device should be 1SG280LU2F50E2VG.
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html
Please let me know if you have any concern.
Regards,
Vikas
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Thanks for your reply. Actually I think I found the model on the dev kit guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-fpga-devl-kit.pdf. And it is verified by my experiments in configuring the board.
Please also see my related question: https://forums.intel.com/s/question/0D50P00004FAIJoSAP/stratix-10-development-board-failed-to-load-configuration
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Hi Xiaowei Wang,
Could you please check the below KDB link for the issue you have?
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2018/jtag-configuration-failure-due-to-improper-pmbus-slave-mode-sett.html
I hope it may help to you.
Regards,
Vikas
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