I2C on stratix 10 GX devkit

[SDe_J]

Hello,

I have a Stratix 10 GX development kit (This one: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx.html)

I'm trying to use the I2C connection between the Stratix 10 FPGA and the SI5341A to program the clocks. I know I can do this via the Board test system, but I'm interested in learning more about I2C communication and this seems like a good testbench.

I have an I2C master implementation in VHDL. I have connected the SDA and SCL lines to the pins named LT_IO_SDA and LT_IO_SCL in the schematic (FPGA pins V22 and V21). I'm also using signaltap to see what's happening on the FPGA.

What I'm seeing is that these SDA and SCL are both fixed at '0'. From what other experience, I understand that I2C lines are held high when idle.

Is there something that I'm missing somewhere? A setting of switch that needs to be set to use the LT_IO I2C lines?

Thank you for your assistance.

[FvM]

Hi,

if you review DevKit schematic, you'll notice that LT_IO_SDA and LT_IO_SCL are by default disconnected from LT_I2C bus, see page 6.

Jumpers R5295/R5296 aren't populated. An I2C controller connected to LT_IO_I2C must implement multi-master features to cooperate with SDM power manager.

Regards
Frank