IO pins status before and during Cyclone V device power-up initialization

[AKaga2]

I recognized that before Cyclone V FPGA device being initialized (immediately after power-up) there is some voltage on its IO pins (not Z-state that expected). How to prevent appearance of these parasitic signals that cause PCB problems?

[Rahul_S_Intel1]

Hi ,

As per the cyclone V power management guidelines.

the Cyclone V device does not drive signals out before or during power up, the device does not affect the other operating buses. 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Page no: 317

And I felt like may be the below scenario could have happened

device uses GND as a reference for hot-socketing and I/O buffer circuitry designs. To ensure proper operation, connect GND between boards before connecting the power supplies. This prevents GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled up GND could otherwise cause an out-of-specification I/O voltage or over current condition in the Altera device.