Inconsistent Data on UART output terminal from Sockit Cyclone V SoC board

[matif]

With reference to my case (case no. 04274941) (https://forums.intel.com/s/question/0D50P00004OYyjkSAD/inconsistent-data-of-transceiver), I am having inconsistent data onto my UART output terminal (PUTTY on Windows 10 host machine). I have checked my design using Quartus 2 Signal tab logic analyser and my HDL results are perfectly fine. My Transceiver is running on 62.5MHz clock while I am running Linux on my cyclone V SoC board and I think that the Linux application that I wrote to read data is running much slower. Is there any way to see the consistent transceiver data. You can see whole progress of my work and discussion here (https://forums.intel.com/s/question/0D50P00004OYyjkSAD/inconsistent-data-of-transceiver)

[EBERLAZARE_I_Intel]

Hi,

May I know what is the Linux application that you wrote to read the data or did you get it from an example somewhere?

Regards.

[matif]

Hi, thank you so much for your answer. I wrote my Linux application in C language. It is attached herewith. I am accessing UART Output terminal using PUTTY on Windows 10 with baud rate 57600. Here are Details of my Linux operating System that I am using on my cyclone V board Linux : Poky 8.0 (Yokto Project 1.3 Reference Distro) Kernel Version: 3.7.0 Sent from Mail for Windows 10

[EBERLAZARE_I_Intel]

Hi,

I did not find the attached file, can you re-sent them again?

Thanks.

[matif]

Hi @EberL_Intel​ 

Sorry for late reply. I was ill during the whole week that is why couldn't reply you. Can you send me your email address so that I can send you the files. The c code I have attached herewith

#include <stdio.h> #include <unistd.h> #include <stdlib.h> #include <stdint.h> #include <fcntl.h> #include <sys/mman.h> #include <sys/types.h> #include <sys/stat.h> #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\hwlib.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\socal.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\hps.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\alt_gpio.h" #include "D:\masterarbeit3\XCVRPUTTYSIM\hps_0.h"   #define REG_BASE 0xFF200000 /*LWFPGA SLAVE Address*/ #define REG_SPAN 0x00200000   volatile unsigned int *reg_addr; /*this is the pointer that reads from the register*/ void* virtual_base; /*pointer to open device memory file*/   int main () { int fd = EXIT_FAILURE;   fd=open("/dev/mem",(O_RDWR|O_SYNC)); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } printf("fd is ok\n");   virtual_base=mmap(NULL,REG_SPAN,(PROT_READ|PROT_WRITE),MAP_SHARED,fd,REG_BASE); printf("virtual base pointer to open device memory file is ok\n");   reg_addr = (unsigned int *) (virtual_base+NEW_COMPONENT_0_BASE); /*accessing base address of register*/ while(1) { printf("pointer value is %d\n", *reg_addr); } return 0; }

[EBERLAZARE_I_Intel]

Hi,

I would like to know if you still facing the inconsistent issue?

[matif]

Hi

Thank you so much for your follow up. Everything is fine now. You can close this case.