I am using Intel's Arria10 SoC Dev kit. I loaded the PCIe design example from the IP catalog. I was able to program the board ok. I attached the board to my PC via a PCIe cable. The PC is unable to recognize the board. I tried this board on another PC and it came up ok. What could be the cause that my PC is unable to recognize it? How can I debug this?
Yes, I programmed the FPGA but did not restart the PC. But I tried restarting the PC for a different reason and found the PC could not reboot when the FPGA board was powered up.
The issue turned out to be the PCIe slot. I had the adapter cable in a x4 slot. I moved it to a x16 slot and it was ok atleast for Gen2. The PC is PCIe Gen3 but the PC does not load the card under device manager for any Gen3 setting in the IP design example. Also, as you mentioned I had to restart the PC after programming to make the PC scan for the PCIe device. But my colleague is able to scan the device without restarting the PC. Both of us are using Windows 10 just different motherboards. Is there a BIOS setting for this? I couldn't find one but read there is a ACPI setting for hot plug. Do you know? Also, why is Gen3 not working? The other issue is the PCIe test is not passing (Altera_PCIe_Interop_Test from the IP core directory in Quartus folder). The test is able to get all the PCIe details like Hardware ID properly.
Looking at the video in the link, I am following all the steps as is. Still no luck with the hardware test. Will the example work for other design kits also by selecting "none" in the example design tab? The simulation itself works.
Under Device Manager, Altera PCI device, Events-Information, I see the message below even though the driver is shown to be installed and working properly. Why is that? I notice that x8 config doesn't work for Gen1 to 3. I think even x4 is not working but x2 is working. Could it have something to do with the message below?
Device PCI\VEN_1172&DEV_0000&SUBSYS_00000000&REV_00\4&2db3ecda&0&0008 requires further installation.
To understand the difference, we may need to know what is the difference in term of PERSTn timing, and when the refclk is start to stable for difference slot.