Intel FPGA Terrasic DE10 standard Cyclone V freeRTOS

[Saud10]

I've trying to do the Cyclone V FreeRTOS tutorial on DE10-Standard (https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/Altera/RTOS_Altera_SoC_ARM_Cortex-A9)

So far I have resloved alot of issues such as:
1. Adding all the include paths.
2. Getting the toolchian arm-altera-eabi from an older version of ARM DS-5.
3. Excluding "alt_interrupt_armcc.s" from the build process.
4. Added all the compiler and linker flags.
5. Resolved some of the issues in FreeRTOSConfig.h

The project compiles and go through the build process successfully, but once I start debugging the code on the board I get the following error:

Stopping running target Intel SoC FPGA - Cyclone V SoC (Dual Core) on connection
Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
Execution stopped in SVC mode at S:0xFFFF2C5C
S:0xFFFF2C5C B {pc} ; 0xffff2c5c
cd "/home/e/developmentstudio-workspace"
Working directory "/home/e/developmentstudio-workspace"
Execution stopped in SVC mode at S:0xFFFF2C5C
source /v "/opt/arm/developmentstudio-2023.1/sw/debugger/configdb/Scripts/altera_target_check.py"
S:0xFFFF2C5C B {pc} ; 0xffff2c5c

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "/home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset
+wait 5s
Target has been reset
Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Using the LLVM DWARF Parser for this file /home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot-socfpga/spl/u-boot-spl
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFFBAB3 (size 0xBAB4)
Loaded section .rodata: S:0xFFFFBAB4 ~ S:0xFFFFDE0B (size 0x2358)
Loaded section .data: S:0xFFFFDE0C ~ S:0xFFFFDEB3 (size 0xA8)
Loaded section __u_boot_list: S:0xFFFFDEB4 ~ S:0xFFFFE6F3 (size 0x840)
Entry point S:0xFFFF0000
+set semihosting enabled true
Semihosting server socket created at port 8000
+set debug-from *$entrypoint # Set start-at setting to address of $entrypoint
+start
Starting target with image /home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/uboot-socfpga/spl/u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000
In boot0.h
S:0xFFFF0000 10,0 ARM_VECTORS
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF0D1C
on file spl_gen5.c, line 35
+cont
+set semihosting enabled true
+wait 10s
ERROR(CMD360):
# in /home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds:50 while executing: wait 10s
! Wait for stopped timed out
ERROR(CMD656): The script /home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/preloader.ds failed to complete due to an error during execution of the script
loadfile "/home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Debug/RTOSDemo.elf"
Using the LLVM DWARF Parser for this file /home/e/de10/FreeRTOS-8.2.2/FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/Debug/RTOSDemo.elf
ERROR(CMD16-TAD11-NAL33):
! Failed to load "RTOSDemo.elf"
! Failed to write 8 bytes to address N:0x0010C330
! Target is running, cannot access.
set debug-from main
start
ERROR(CMD350): Command not possible when running
wait

[Jeet14]

Hi,

I suggest that you get support from FreeRTOS forum support on their website as this example is provided by the FreeRTOS.

Regards

Tiwari

[Jeet14]

Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.