We are currently working with the Intel Cyclone 10 GX Development Kit FPGA and considering the integration of the C10 GX with one of our solutions. Following the interface and block diagram we have noticed that there are two Max 10. One acting as an on-board download cable II for C10 GX programming and another one as host for configuration through a NOR flash memory (also responsible for other tasks such as clock configuration or serial communication for sensing).
We would like to preserve the Max10 as on-board USB blaster on the JTAG chain since we consider it practical for portability, instead of having an external one. However, the documentations only mentions and provides the code for the configuration Max10 interfacing with the flash memory. We were wondering if the code of the first one is available to the customers?
We appreciate your support,
Altera, in the past, have only shared this design with approved partners, such as Terasic. I suspect Intel's position is the same.
Don't expect to be able to get hold of the design information required to support and on-board USB-Blaster configuration CPLD for your design.
Intel Max10 as On-Board Intel FPGA Download Cable II required license.
Thus, you need to purchase license in order to the On-Board Intel FPGA Download Cable II Code.
Thanks for your kind answers. This is an interesting feature we would like in our design so we will consider acquiring the license shortly in the future. Thanks again.