Intel socFpga Agilex 7 security features case(authentication, en/decrypt, hash, customer defined se)

[wuhr]

we will develop security features based on Agliex 7, we need some referrence code, doc, menu for fpga/hps image sign/verify, encrypt/decrypt, hash and some customer defined security services, and some questions below:

  - how to program efuse without JTAG

  - User defined fuses size: we can only read 16 words(32bit), but doc says there are 32 words(32bit).

  - what's the using scenario for EFUSE/BBRAM/PUF?

  - what's BBRAM's battery life expectancy?

  - how Agilex 7 SDM prevent EFUSE illegall copy?

  - can signed fpga bitstream work on disabled security fpga board?

  - can we get fpga chip id without power on chip?

[wuhr]

- provide Black Key Provisioning Service Distribution

[Farabi]

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[Farabi]

Hello,

referrence code, doc, menu for fpga/hps image sign/verify,

encrypt/decrypt, hash and some customer defined security services

You can find all the information from : https://www.intel.com/programmable/technical-pdfs/683823.pdf

AN968 : Black Key Provisioning (link : https://www.intel.com/content/www/us/en/secure/content-details/739071/an-968-black-key-provisioning-service-quick-start-guide.html?wapkw=AN968)

 - how to program efuse without JTAG :

<ANS>efuse is programmed through SDM

- User defined fuses size: we can only read 16 words(32bit), but doc

says there are 32 words(32bit).

<ANS> eFUSE size is 2048bits(256bytes)

 - what's the using scenario for EFUSE/BBRAM/PUF?

<ANS> Military, IP protection

 - what's BBRAM's battery life expectancy?

<ANS> at least 2 years.

 - how Agilex 7 SDM prevent EFUSE illegall copy?

<ANS> no access to SDM

 - can signed fpga bitstream work on disabled security fpga board?

<ANS> No

 - can we get fpga chip id without power on chip?

<ANS> No. Chip ID need to access during user mode.

rgards,

Farabi