Issue regarding reading the Analog value from ADC

[mwac__]

Hi.

I'm working on Altera Cyclone V,SOC DE1 (rev F) board. I need to access the on board available ADC (LTC 2308). The software version I'm using is Quartus ii(13.0,64 bit). The simulation waveform generated by the test bench is exactly matches the one mentioned in the datasheet.
While hardware demonstration, I've tried to show the 12 bit data using LEDs. The LEDs shows the same fixed pattern even if I change the Analog input value.

I'd highly appreciate if someone assist me to additional the issue.


Thank you.

[khtan]

Hi,

Thanks for reaching out to us. I'm Kian and will be looking into your case.

Just some basic question first for debugging:

1. Could you confirm that does the 12bit data output from ADC changes according to the voltage/signal input to the ADC ? Just to check whether the ADC is giving values out or doesn't change at all.

2. If modify your program instead of relying on the 12bit ADC data to a simple counter to change the LEDs, does the LEDs change? This is just to confirm the LEDs are configured correctly and can be controlled in your program.

Meanwhile I will check whether we have some examples or documents that could help in this case.

Thanks

Regards

Kian

[khtan]

Hi,

These are the few documents that I found, not sure whether you already have the manual documentation and design as they have the design for reading the ADC and also triggering the LEDs

For ADC usage and implementation, you can refer to the Terasic DE1 SOC manual page 83 and example design provided by Terasic

Manual:

https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=836&FID=3a3708b0790bb9c721f94909c5ac96d6https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=836&FID=ae336c1d5103cac046279ed1568a8bc3

Design files for the demo (select ref F):

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836&PartNo=4

Document on ADC (its based on Quartus 18 but still applicable)

https://ftp.intel.com/Public/Pub/fpgaup/pub/Intel_Material/18.1/University_Program_IP_Cores/Input_Output/ADC_Controller_for_DE_Series_Boards.pdf

Thanks

Regards

Kian

[mwac__]

Well, I genuinely admire the time you've invested in. But the issue I encountered was bit different. Though the test bench generated the exact timing diagram that was required to program an ADC. But when I used the Signal Tap analyzer, it happened to me that the latch of logic 1 was generated at the ADC_DIN pin due to which channel 07 of ADC was selected at the start of each conversion. The difference between test bench and Signal Tap Analyzer behaviour was quite surprising for me. When I modified the code a bit, the Correct channel of ADC has been configured.

Thank You. 

[khtan]

Hi, 

Sorry for the delay in replying, was in a 3 day offsite training. Glad that your code is working now, as for your question on the Testbench simulator,  I was discussing with my colleague here on this case and we suspect that you might need to add in latency manually to simulate close to real work situation even though the simulated waveform is matching to the one specified in the guide. I wonder whether Terasic would have more information on this since they build the custom DE 1 SOC board.

Thanks

Regards

Kian

[khtan]

Hi,

Is there any further question related to this forum case? Otherwise I would like to close and transition the thread to community support.

Thanks

Regards

Kian

[mwac__]

Sure thing. The issue has been fixed. You may close the discussion on the topic.

Warm Regards.

[khtan]

Hi,

I will proceed to close the case and transition it to community support.

Thanks for contacting Intel.

Regards,

Kian