02-01-2010 01:14 AM
Hello,I am using an Arria I dev kit to interface to a board that contains 3 FPGAs. The interface (HSMC) provides a JTAG connection plus a number of I/O that I will be using to do PS configuration for all 3 chips. The I/O standard from the HSMC is 2.5V but all the I/O standards on the 3 FPGAs are 3.3V. My questions are: 1. Will the JTAG and Config work even if there is an I/O voltage mismatch? According to the specs, either side should tolerate the VIH levels. 2. Do I need to use a level shifter like Altera does in other dev kits? 3. Can I rely on controlling the drive strength of the I/O (used for PS config) coming from the dev kit to get better signal integrity or should I add series terminations? Thank you for you help!
02-01-2010 05:26 AM
1 & 2 - What are the three FPGAs on the other board? More than likely, you'll be just fine between 2.5V and 3.3V. If you were going down to say 1.8V, you might have trouble.3 - I think you'll be fine with the on-chip current strength selection. This is a dev kit right? Adding a series resistor can actually hurt you if it's not in the right position (close to the driving pin). Jake
02-01-2010 07:44 AM
Jake, thanks for the answer!Good point on 3. The termination should be at the source and I am quite far from it (in signal terms.) The other 3 FGPAs are Arrias (I) also.
02-01-2010 04:36 PM