I have code which instantiates a particular design N no. of times.
When the N>12000 , even though the Quartus tool generates the bitstream, I am not able to configure the FPGA on board(DE1-SoC). Even after programming the new bitstream through JTAG , the board automatically loads the bitstream from serial flash. How and why is this happening? Any suggestions to workaround this?
Thanks & Regards,
I am using .sof file for programming and I am not power cycling after programming. Do you know the reset condition for this board and where it is mentioned?
I am suspecting the board is resetting and then programming the FPGA in default mode which is from the flash.
For n<12000 the FPGA programming happens as expected. In my design there is no logic of resetting . Infact I am not using HPS part of the device only PL part.
What I observed is for n>12000 the resource utilization goes above 50%. Will that cause a problem?