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Hi,
I would like to look at the eye diagrams of a QSFP-DD800 module driven with an Agilex 7 FPGA DevKit using a Keysight DCA, which requires a subrate clock of the data.
Do any of the Agilex 7 FPGA DevKit boards have an SMA output with a clock that is coherent with the data?
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Hi,
May I know which device part you are trying to use? Or which Tile, F-tile, R-tile, E-tile or P-tile?
Regards
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Hi,
Any update on my previous comment? May I know what you are looking for.
Regards

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