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Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Exemple on the board Stratix 10 SX SoC dev

Convers
Novice
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Hello,

 

We are trying to use the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Exemple on the board Stratix 10 SX SoC devkit (H-Tile version).

When we connect the board with QSFP28 cable on the J10 connector to another device, we didn’t get the Word Lock. More details are explained below.

 

We are using Intel Quartus prime pro 23.1.

First, we generated the Design Example for the Stratix 10 GX Devkit, and we adapted this design (Pinout and device option) to correspond to our board Stratix 10 SX SoC devkit.

The design compilation is successful without errors.

 

When we test the design by using Ethernet toolkit and enabling the Serial PMA Loopback, it works well. We get the Word Lock and all the design indicators seem to be going well.

 

After we disable the Serial PMA Loopback and we connect the QSFP28 on J10 connector to another device (Alveo U250), it doesn’t work.

In the Ethernet toolkit, we get:

-          TX Clock (kHz): 390630   and   TX Core Clock stable: Yes

-          RX Clock (kHz): 390630   and   RX Core Clock stable: Yes

This part looks good and the results are as expected. The other PLL are also locked.

But the other parameter below, is not as expected:

-          Word Lock: 0x00000000

-          Frame Error: 0x000fffff

-          Lanes Deskewed: No

-          Alignment Marker Lock: No

-          RX PCS Ready Ready: No

 

Moreover, we tried to connect to another device, we replaced the Alveo U250 with an Intel E810 board. And in this case it is worse than before because we don't get the RX Core Clock stable.

For information, the 100G link between Alveo U250 and Intel E810 is working well.

 

Last but not least, the QSFP28 cable we use is a FLAXOPTIX Q.C261HG.3 and it has been configured in a symmetrical way to allow us to establish a solid link between the Intel E810 board and the Alveo U250. However, we are not sure if the current setup is fully compatible with the Stratix 10 SX. Does anyone know what kind of cable configuration is required for the Stratix 10 SX devkit?

 

If there is some recommendation or idea why is it not working? It is welcome.

 

Thanks for your help.

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Convers
Novice
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Hello,

 

Finally, we find the solution and we share it, if it can help someone.

 

The problem was the FEC option. It was enable on the Alveo U250 and also on the Intel E810.

As soons as we aligne that on each side it works (Disable FEC on both side OR Enable FEC on both side). 

 

Regards

Anthony

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Convers
Novice
371 Views

Hello,

 

Finally, we find the solution and we share it, if it can help someone.

 

The problem was the FEC option. It was enable on the Alveo U250 and also on the Intel E810.

As soons as we aligne that on each side it works (Disable FEC on both side OR Enable FEC on both side). 

 

Regards

Anthony

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