Non-volatile programming on Stratix 10 TX Signal Integrity Kit

[michaelheartsintl]

Looking for assistance on an issue that seems like it should be a no brainer. Trying to get the Stratix 10TX signal integrity dev board to load our image at boot so we don’t have to soft flash.

I’m attempting to flash either the 1. EPCQL flash or the 2. AvSTx16 memory controlled by the MAX 5 CPLD so the FPGA will load our program at boot.

When I try the EPCQL flash route with a .jic file to indirect JTAG program, I get the message that the factory SDM image isn’t supported. This is the path I’m used to following, but haven’t hit this compatibility issue before – is this a Stratix10 issue?

I’ve also tried generating a .pof for the AvSTx16 load route (which appears to be what documentation indicates I should be using, though the EPCQL is present).

I’ve successfully programmed the memory, my DIP settings are for AvSTx16, and regardless of whether I toggle the FACTOR_LOAD or USER pof, the MAX_ERR LED always come on – never the MAX_CONF_DONE, so it looks like the MAXV is simply failing to configure the FPGA regardless of what I do.

Any thoughts, or anyone done this before?

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

Apologize for the delay in response.

Can you used the factory default setting and try to program again? Do not modify anything.

You can refer to the dev kit userguide.

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you