Re: PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Pa1_bhandari · ‎05-03-2019

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add pcie hard ip pin's in device, with integrated two hard ip's the synthesis is not passing, can any one help me out to solve this issue.

Thanks

Pavan

Nathan_R_Intel · ‎05-06-2019

Hie, You can try using the example design in the following links as a reference to build your design: https://fpgawiki.intel.com/wiki/Reference_Design:_Gen2x4_AVMM_DMA_-_Cyclone_V Also, please refer to our user guide on how to build the PCIe reference design for Cyclone V. The links for the user guide are below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf Regards, Nathan

Pa1_bhandari · ‎05-06-2019

Dear Nathan,

Many thank's for the link's which you have sent.

Actually We are in the initial stage of project were we need to share ".pin" file to Board team.

When we try to do assignment with early pin planning for PCIE we are facing the issue related to compilation .

When we assign other pins we don't have issue.

Can you help us on this ?

Thanks and regards

Pavan Kumar

Nathan_R_Intel · ‎05-07-2019

Yes. I can help. However, I need more details such as pin placement and your observed compilation error to assist you. Please specify which channels are used as XCVR and TX PLL. Example is: GXB_L0_CH5 - unused GXB_L0_CH4 - PCIe Channel 3 GXB_L0_CH3 - PCIe Channel 2 GXB_L0_CH2 - PCIe Channel 1 GXB_L0_CH1 - Tx PLL for PCIe GXB_L0_CH0 - PCIe Channel 0 Also, for PCIe channel placement, please read up this section in our handbook. It could also self-help you to addresss the PCIe channel placement issue. Please refer to "PCIe Supported Configurations and Placement Guidelines" in Pg 4-7 (Pg 116/171) in : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Regards, Nathan

Pa1_bhandari · ‎05-07-2019

Hi Nathan,

Thanks for the links and information regarding channels.

1.We are planning to use X1 and X2 for two PCIe Endpoints.

2.Can we generate a IP with X2 lane support and instantiate them and keep the one of the lane unused .

3. Following are the pin assignments we are planning to use .

Bank Number | Location |

—————————————————————

GXB_L2 GXB_TX_L7n M3 PCIE _EP1_TX[1]_N

GXB_L2 GXB_TX_L7p M4 PCIE _EP1_TX[1]_P

GXB_L2 GXB_Rx_L7n N1 PCIE _EP1_RX[1]_N

GXB_L2 GXB_RX_L7p N2 PCIE _EP1_RX[1]_P

GXB_L2 GXB_TX_L6n P3 PCIE _EP1_TX[0]_N

GXB_L2 GXB_TX_L6p P4 PCIE _EP1_TX[0]_P

GXB_L2 GXB_Rx_L6n R1 PCIE _EP1_RX[0]_N

GXB_L2 GXB_RX_L6p R2 PCIE _EP1_RX[0_P

GXB_L2 REFCLK2Lp P8 PCIE _EP1_REFCLK_N

GXB_L2 REFCLK2Ln N7 PCIE _EP1_REFCLK_P

Regards

Pavan

Pa1_bhandari · ‎05-07-2019

Adding one more query is it possible to assign only IO's for PCIE HARD IP and do Analysis to generate the ".pin" file for the board team.

When we try the above step we are getting the compilation error as below

Error (177035): The input pin PCI_EP0_REFCLK_P assigned to HSSI Pin_W8 has no fanout.

Error (177035): The input pin PCI_EP0_REFCLK_N assigned to HSSI Pin_W7 has no fanout.

Error (177035): The input pin PCI_EP0_RX_P[0] assigned to HSSI Pin_AG2 has no fanout.

Error (177035): The input pin PCI_EP0_RX_P[1] assigned to HSSI Pin_AE2 has no fanout.

Error (177035): The input pin PCI_EP0_RX_N[0] assigned to HSSI Pin_AG1 has no fanout.

Error (177035): The input pin PCI_EP0_RX_N[1] assigned to HSSI Pin_AE1 has no fanout.

Error (177035): The input pin PCI_EP1_REFCLK_P assigned to HSSI Pin_N7 has no fanout.

Error (177035): The input pin PCI_EP1_REFCLK_N assigned to HSSI Pin_P8 has no fanout.

Error (177035): The input pin PCI_EP1_RX_P[0] assigned to HSSI Pin_R2 has no fanout.

Error (177035): The input pin PCI_EP1_RX_P[1] assigned to HSSI Pin_N2 has no fanout.

Error (177035): The input pin PCI_EP1_RX_N[0] assigned to HSSI Pin_R1 has no fanout.

Error (177035): The input pin PCI_EP1_RX_N[1] assigned to HSSI Pin_N1 has no fanout.

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error: Quartus Prime I/O Assignment Analysis was unsuccessful. 13 errors, 13 warnings

Error: Peak virtual memory: 5625 megabytes

Error: Processing ended: Tue May 07 17:54:45 2019

Error: Elapsed time: 00:00:16

Error: Total CPU time (on all processors): 00:00:16

Nathan_R_Intel · ‎05-08-2019

Hie, Please check my replies to your questions: Question: 1.1.We are planning to use X1 and X2 for two PCIe Endpoints. Answer: Yes this can be supported. However, you need to place the x1 and x2 in different PCIe Hard IP (HIP). You will need to use both the PCIe Hard IP (HIP) available in your device. Please refer to Table 4-2 in handbook to determine if your device supports both x1 and x2 configuration. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Question: 2.Can we generate a IP with x2 lane support and instantiate them and keep the one of the lane unused . Answer: Yes you may. If only a x1 is connected on the other end, the PCIe link will down-configure and run x1. Question: 3. Following are the pin assignments we are planning to use . Answer: The pin assignment seems correct. You are using the upper HIP. However, please get Quartus Prime to complete compilation to 100% be certain the channel placement is correct. As I explained above certain configurations is not supported in the upper/lower HIP based on device. Question: When we try the above step we are getting the compilation error as below Answer: It seems you are not following the channel placement guideline; thus resulting the reported erros. Hence, please refer to "PCIe Supported Configurations and Placement Guidelines" in Pg 4-7 (Pg 116/171) in : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Regards, Nathan

Pa1_bhandari · ‎05-08-2019

Dear Nathan,

Thank you so much for your valuable time and links, i will check them, if i get doubt's i will let you know.

Best Regard's

Pavan

Pa1_bhandari · ‎05-08-2019

@lakshmi.narayanan@blackpeppertech.com @vedashri.parashivamurthy@blackpeppertech.com

Hi Nathan,

As i have assigned top(EP1) with x1 lane and bottom(EP0) with x2 lane.

currently there is no design , only top file with I/O's.

Bank Number | Location |

—————————————————————

EP1

GXB_L2 GXB_TX_L6n P3 PCIE _EP1_TX[0]_N

GXB_L2 GXB_TX_L6p P4 PCIE _EP1_TX[0]_P

GXB_L2 GXB_Rx_L6n R1 PCIE _EP1_RX[0]_N

GXB_L2 GXB_RX_L6p R2 PCIE _EP1_RX[0_P

GXB_L2 REFCLK2Lp P8 PCIE _EP1_REFCLK_N

GXB_L2 REFCLK2Ln N7 PCIE _EP1_REFCLK_P

EP0

GXB_TX_L1n AD3 PCI_EP0_TX_N[1]

GXB_TX_L1p AD4 PCI_EP0_TX_P[1]

GXB_RX_L1p,GXB_REFCLK_L1p AE2 PCI_EP0_RX_N[1]

GXB_RX_L1n,GXB_REFCLK_L1n AE1 PCI_EP0_RX_P[1]

GXB_TX_L0p AF4 PCI_EP0_TX_P[1]

GXB_TX_L0n AF3 PCI_EP0_TX_N[0]

GXB_RX_L0p,GXB_REFCLK_L0p AG2 PCI_EP0_RX_N[0]

GXB_RX_L0n,GXB_REFCLK_L0n AG1 PCI_EP0_RX_P[0]

REFCLK0Lp W8 PCI_EP0_REFCLK_P

REFCLK0Ln W7 PCI_EP0_REFCLK_N

Error (177035): The input pin PCI_EP0_RX_N[0] assigned to HSSI Pin_AG1 has no fanout.

Error (177035): The input pin PCI_EP0_RX_N[1] assigned to HSSI Pin_AE1 has no fanout.

Error (177035): The input pin PCI_EP1_REFCLK_P assigned to HSSI Pin_N7 has no fanout.

Error (177035): The input pin PCI_EP1_REFCLK_N assigned to HSSI Pin_P8 has no fanout.

Error (177035): The input pin PCI_EP1_RX_P[0] assigned to HSSI Pin_R2 has no fanout.

Error (177035): The input pin PCI_EP1_RX_N[0] assigned to HSSI Pin_R1 has no fanout.

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device.

Thanks and Regards

Pavan

Nathan_R_Intel · ‎05-28-2019

Hie, My apologies for the delayed response. I missed your last response. Could you please provide your design achieve (.qar) so I can check whats causing the issue. You channel placements seems correct. Regards, Nathan

Nathan_R_Intel · ‎06-18-2019

Hie, Could you please provide your design achieve (.qar) so I can check what is causing the issue. Current;ly, your channel placement is correct. I need information how is the IP components connected in the design to understand the failure. Regards, Nathan