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Pcie loopback in the end point

srinivasan
Beginner
1,343 Views

Hello sir,

         I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end point(other device). For that I need to configure the TS1 Loopback bit set in the root complex to enable loop back mode at the end point.

   Here My query is how/where I need to set the TS1 loopback bit in the Pcie root complex design to  enable loop back at the end point.So Please share me the Corresponding Registers and steps need to be followed in the Design. If possible please share the End point loop back and root complex reference design.

 

 

Regards,

Srinivasan.

      

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14 Replies
KFPW_Intel
Moderator
1,323 Views

Hi,

 

Thank you for your interest in Intel® SGX.

 

We are here in Intel® SGX community forum and I believe you are looking for Arria 10 PCIE support. I am going to transfer the question to a correct community forum for more information.

 

Allow us to refer to a correct team and the team will assist you and your question further. Thank you.

 

Regards,

Ken


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wchiah
Employee
1,318 Views

Hi,


For Arria 10 root port design you can get it at below

https://www.rocketboards.org/foswiki/Projects/Arria10PCIeRootPortWithMSI


Regards,

Wei Chuan


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srinivasan
Beginner
1,303 Views

Hello sir,

     Just tell how to access the TS1 loopback set bit in the rootcomplex design to enable the loopback at the end point...Pls send the configuration registers.

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wchiah
Employee
1,291 Views

Hi,

I think this is what you looking at.
Please correct me if I am wrong, 
https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/enabling-and-disabling-loopback-modes.html

let me know if this is helpful.
Regards,

Wei Chuan

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srinivasan
Beginner
1,117 Views

Hi,

      This register is not supported for the pci loop back.Can u please send me the Actual registers for pcie loopback at the end point.

 

Atleast ,share the  RTL code for the configuration register set for pci root complex. 

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srinivasan
Beginner
1,283 Views

Thanks for the reply,

     Hello chuan,

             What you shared is correct, but I want to send the loopback configuration packet from the root complex design to end point.

Please send the screenshot of the loopback register used  in the implemented root complex design.

 

 

Note:   End point should be in loopback mode

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wchiah
Employee
1,275 Views

Hi,


I dont really get your question , Can you describe more detail ? 
Do you means that the document does not address what you want or other 

Regards,

Wei Chuan

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wchiah
Employee
1,146 Views

Hi,

If you want to know how to set the loopback mode, Please refer to Arria 10 Soc User guide under Section 4.13
https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/soc/es2_files/A10-SoC-DK-UG_2.pdf

 

Let me know if this answered your question.


Regards,

Wincent_Intel

 

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wchiah
Employee
1,192 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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srinivasan
Beginner
1,178 Views

Hi,

    Finally,  Please send the Configuration loopback register access RTL code  for root complex design.

 

Note: Not whole design, only configuration RTL code(Verilog/VHDL file).

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wchiah
Employee
1,129 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
1,107 Views

Hi


If you are using JESD204B serial loopback, there are two ways to enable. 

1. there is a port in the IP interface, you can assert to enable the serial loopback mode.

2. You can use the reconfig interface as you describe in the case, actually there is no base address, but you should use the reconfig avmm interface, not the JESD204B csr avmm interface, the address for each channel is 0x2000, so the first channel base address is 0x0, and the second address is 0x2000, third 0x4000, and so on. 


Hope this answer your question.

Regards,

Wincent_Intel


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wchiah
Employee
1,068 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
977 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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