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Hi all,
when writing data from .yuv file stored on PC to DDR SDRAM Memory using C routine(Data Capture Routine considering syncs) from NIOS II, i am not able to read data more than 32 pixels.Can anyone let me know waht might me the problem. and the code is fine as far as logically.Is there any option or settings we have to in NISO II IDE or Board to solve this? or is there a limitation of nIOS II Board(Stratix II fs2s60) please let me knoe ASAP.It urgent thanks in Advance santosh The C code is as follows: # include <stdio.h> //#include <math.h> # define SDRAM_ADD1 0x02000000 //012110C0 //0800 0000 # define SDRAM_ADD2 0x021fe000 //0140F0C0 //081FE000 # define Frame_flag 0x024fc000 # define Frame_flag_Calc_done 0x024fc010 # define pic_width 13 # define pic_height 3 # define num_of_seq 4 FILE *fp_input; FILE *fp_output; unsigned int pic_count = 0; unsigned int i=0; unsigned int j=0; unsigned int cnt; void data_capture(unsigned char *Hsync,unsigned char *Vsync, unsigned char *data_en, unsigned char *start,unsigned char *stop); int main() { unsigned char ch,ch1[100],add_change_flag = 0; unsigned char Hsync=0,Vsync=0,data_en=0,start=0,stop=0; unsigned int Hcount=0,Vcount=0,frame_size=0; unsigned int width,height,i=0; unsigned int pic_count_in=0,pic_cnt=0; unsigned char *ptr = SDRAM_ADD1; unsigned char *ptr_temp = SDRAM_ADD1; unsigned int *ptr_flag = Frame_flag; unsigned int *ptr_flag_Calc_done = Frame_flag_Calc_done; // = 0; *ptr_flag_Calc_done = 0; fp_input = fopen("/mnt/host/aa.yuv","rb"); if(fp_input) { printf("\n File opened"); } fp_output = fopen("/mnt/host/Out.yuv","wb"); if(fp_output) { printf("\n File opened"); } while(1) { data_capture(&Hsync,&Vsync,&data_en,&start,&stop); if(start) { printf("\n Start Signal received"); break; } } while(1) { data_capture(&Hsync,&Vsync,&data_en,&start,&stop); if(Vsync) { printf("\n Vsync received \n"); Vsync = 0; break; } } while(1) { data_capture(&Hsync,&Vsync,&data_en,&start,&stop); if(data_en) { width = Hcount; Hcount++; } if(Hsync) { Hcount = 0; Hsync = 0; height = Vcount; Vcount++; } if(Vsync) { Vsync = 0; break; } } printf("\n %d %d",*ptr_flag_Calc_done,Frame_flag_Calc_done); frame_size = width * height; *ptr_flag_Calc_done = 1; *ptr_flag = frame_size; //*ptr_flag_Calc_done = Frame_flag_Calc_done; printf("\n %d %d",*ptr_flag_Calc_done,Frame_flag_Calc_done); printf("\n %d %d",ptr_flag,frame_size); while(1) { data_capture(&Hsync,&Vsync,&data_en,&start,&stop); if(stop) { break; } if(data_en) { ch = fgetc(fp_input); *ptr = ch; ptr++; printf("\t %d %d",ptr,ch); if(ptr - ptr_temp == frame_size) { add_change_flag = !add_change_flag; if(add_change_flag) { ptr_temp = SDRAM_ADD2; //pic_count_in++; } else { ptr_temp = SDRAM_ADD1; //pic_count_in++; } ptr = ptr_temp; } //pic_count_in++; } //pic_count_in++; } printf("\n Pic Count %d",pic_count); //Reading from DDR Starts ptr = SDRAM_ADD1; ptr_temp = SDRAM_ADD1; add_change_flag = 0; /*do { do { printf("\n Started reading data from DDR \n"); ch1[i] = *ptr; ptr++; i++; //fputc(ch,fp_output); printf("\n read one data from DDR \n"); }while(ptr - ptr_temp < frame_size); i=0; fwrite(ch1,sizeof(char),frame_size,fp_output); printf("\n Pic No %d",pic_cnt); printf("\n comes out \n"); add_change_flag = !add_change_flag; if(add_change_flag) { ptr_temp = SDRAM_ADD2; pic_cnt++; } else { ptr_temp = SDRAM_ADD1; pic_cnt++; } //pic_cnt++; }while(pic_cnt < (pic_count - 2));*/ //Reading from DDR Ends fclose(fp_input); fclose(fp_output); return 0; } void data_capture(unsigned char *Hsync,unsigned char *Vsync, unsigned char *data_en,//unsigned char *ch, unsigned char *start,unsigned char *stop) { // unsigned char Hsync=0,Vsync=0,data_en=0,start=0,stop=0; // unsigned char ch; *start = 1; *data_en = 1; // (*ch) = fgetc(fp_input); // cnt++; if(i==pic_width) { *Hsync = 1; i = 0; if(j==pic_height) { *Vsync = 1; j = 0; pic_count++; } else { *Vsync = 0; j++; } } else { *Hsync = 0; i++; } if(pic_count == num_of_seq) { *stop = 1; *data_en = 0; printf(" All data dumped to ddr\n ....\n"); } }Link Copied
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Are you running the FPGA 'Logicware' is the factory default or have you modified the system. If you modified the system, be sure you have the DDR clock setting correct (it needs a slight phase shift).
Mike
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