I am using MaxV device with one pair of LVDS_E_3R. I can compile the design when I don't give any pin location assignment. However after the compile I do back annotation for pin and then when I hit compile, Quartus crashes during fitter run.
Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing
I think the issue is with Pin Assignment. Attached is the QAR. It is a simple MUX.
Apologize for delay in response .
I get a chance to look at your design, but attached file not have any LVDS related IP is added. Can you please confirm the qar file attached ?
Also did you check pin out files what you mapped is correct ? Here is the link for your reference
Thank you ,
sorry missed to attached the line ,
Also here is the link for application notes LVDS_E_3R in MAX V
Thank you ,
The QAR is just a MUX structure. There in no LVDS related IP. I am trying to do a pin placement. The output of the MUX will drive the LVDS receiver chip connected to the CPLD. So two pins on bank 2 of the MAX V CPLD is set to LVDS_E_3R.
If I use Qii11.1 sp2, I don't see any compile error and the same QAR works just fine. But when I try to compile it with Qii18.1 prime (std or lite) , I get the Quartus crash.
i am not sure ...can you try to open the quartus with "Run as Administrator" , BY the way can I know the ram size of your machine ? also Can you uninstall and reinstall the quartus ?