RESERVED_INPUT_WITH_WEAK_PULLUP pins in DE1- Lite

[YigalB1]

I would like to use 3 pins of the 40 pin connector of the DE10-Lite for UART implementation (Tx,Rx,GND).

At first I was thinking of using V10 & V9 because they are top left on the connector, so easy to align. Yet they are far from the GND, so I am thinking now about W7 & V5, because they are near to the GND, so easy to use with 3 pins connector.

However, the pinout table claims they are "RESERVED_INPUT_WITH_WEAK_PULLUP". Does it mean they can't be configured to be 3.3V input and output for the UART needs?

[FvM · Accepted solution]

Hi,

according to DE10-Lite schematic, all GPIO connector pins are connected to RX/TX capable pins in 3.3V IO banks, also questioned GPIO_7 and GPIO_9. I presume, you are seeing "RESERVED_INPUT_WITH_WEAK_PULLUP" in the .pin file of a specific project. It reflects the pin assignments of the design, not the capabilities of the FPGA. "Reserved input" is the assignment of an unused pin. You need to assign intended pins to top level signals in Pin Planner tool or Assignment Editor.

[AqidAyman_Intel]

Yes, @FvM is correct. It is not reflect the device capabilities but rather the assignment for the unused pin. Refer here: https://www.intel.com/content/www/us/en/docs/programmable/683073/current/unused-i-o-pins.html

[YigalB1]

Thank you @FvM and @AqidAyman_Intel for clarifying this. I assigned the pins and the report confirms what you said. 

[AqidAyman_Intel]

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