Reason for low Capacitor count in PDN tool

[KBhag3]

Hi,

I am using the the PDN tool for decoupling capacitors calculation for MAX10 device. I have followed the instructions as per the PDN tool user guide. I am surprised with the very low capacitor count for my design. Can I know if all the inputs provided are OK or any reason for low capacitor count?

Capacitor count will slightly increase if I set Feff to 130MHz as mentioned in the introduction sheet.

Best regards,

Bhagavath

[YuanLi_S_Intel]

Hi Kumara,

After seeing through your PDN sheet, it seems like the power is a little bit abnormal. May i know where do you get the value? Do you get it from our EPE?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/operation-and-testing/power/pow-powerplay.html

Thank You.

[KBhag3]

Hi,

Thanks for your reply & sorry for my delayed response. I was away from office last 3 days.

I did use EPE but I have put power consumption on much higher side as I still don't have the details about FPGA internal resource usage. Can I know which section of the power looks abnormal?

Best regards,

Kumara Bhagavath

[YuanLi_S_Intel]

Hi Kumara,

It would be better if you could put the power value as per the EPE. It will generate an accurate result.

Thank You.