I am using the the PDN tool for decoupling capacitors calculation for MAX10 device. I have followed the instructions as per the PDN tool user guide. I am surprised with the very low capacitor count for my design. Can I know if all the inputs provided are OK or any reason for low capacitor count?
Capacitor count will slightly increase if I set Feff to 130MHz as mentioned in the introduction sheet.
After seeing through your PDN sheet, it seems like the power is a little bit abnormal. May i know where do you get the value? Do you get it from our EPE?
Thanks for your reply & sorry for my delayed response. I was away from office last 3 days.
I did use EPE but I have put power consumption on much higher side as I still don't have the details about FPGA internal resource usage. Can I know which section of the power looks abnormal?