Regarding Ethernet /Transceiver tool kit error in F tile 10G Hard IP for AGFB027R24C FPGA device

[Maitry]

Hello support team, 

We are using AGFB027R24C2I3E Agilex F series FPGA in our custom board. With Bank 13 A, 156.25 MHz (i_refclk2pll_clk) clock is interfaced ( CH6 = CJ7, CH8). And Tx, Rx is in CH1. Also, i_reconfig_clk is taken from CN41, CP40 ( 100 MHz differential ). As this board is custom board for AGFB027R24C2I3E. We have taken a reference example design from quartus 24.2 of F tile 10G hard IP using board type = None, refclk channel -6 and syspll = 322.26 MHz, single instance and generate the project, added above pin mapping and clock settings. and generate .SOF File for 10G. For the validation , We are loopback the SFP module Tx with Rx, load the .SOF file and open In system source and probes editor in which we assert and deassert the source . but there is no indication or changes in the probes. and while opening the ethernet tool kit, we are getting below error.  

Error 1: F-Tile Ethernet Intel FPGA Hard IP: dut_jtag_master
SEVERE: An error occurred while running script "init_toolkit
": F-Tile Ethernet Intel FPGA Hard IP: dut_jtag_master: expected integer but got ""
while executing
"format "0x%x" $gui_option"
(procedure "pysv_package::pysv_callback" line 42)
invoked from within
"pysv_package::pysv_callback"
(procedure "init_toolkit" line 13)
invoked from within
"init_toolkit"

Error 2: F-Tile Ethernet Intel FPGA Hard IP: dut_jtag_master
SEVERE: An error occurred while running script "finalize_toolkit
": F-Tile Ethernet Intel FPGA Hard IP: dut_jtag_master: can't read "master_claim_path": no such variable
while executing
"close_service master $master_claim_path"
(procedure "common_driver_pkg::close_port" line 6)
invoked from within
"common_driver_pkg::close_port"
(procedure "finalize_toolkit" line 5)
invoked from within
"finalize_toolkit"                                                                                                                                                   

Can you provide the feedback and guidance on why We are getting the above error and how to resolve it. 

FYI : My QSFP connector is FTE8510K1LTY. 

[Maitry]

Hello support team, 

Is there any feedback on the above

[Maitry]

Hello, 

By changing CH6 to CH0 in the F tile 10G hard IP, My ethernet tool kit enabled. I have made a loopback. But after enable internal loopback and start reading all status, My Tx PLL lock status is = locked . but My Rx PCS ready status = not ready and Rx CDR locked status = Not locked. 

What is the reason behind this above issue? Is there anything that we are missing over here?

[paveetirrasrie_Intel]

Hi,

Good day to you.

May I know if the reset signals have been deasserted or not? This is because rx_pcs_ready deasserts when i_rx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.

And also I would suggest you to try to generate design example using board type = Agilex devkit and compare the pin assignments to ensure the pin connections is same as devkit.

Regards,

Pavee

[paveetirrasrie_Intel]

Good day.

Just wanted to check with you, any update from your end?

Feel free to let me know if you have further query. Happy to help.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.