This question is regarding the maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board.
We did the following tests:
A) Using the streaming_dma_afu example for bandwidth. - 6.7 GBps read, 7.6 GBps write
B) Using the nlb_mode_0 example in LPBK1 mode. - 9 to 9.5 GBps
C) Using OpenCL based 'aoc diagnose all'. - 8.4 GBps
Could someone please let us know why the achievable bandwidth in these tests is almost half of the official specification?
Thank you for your response. I agree that data transfer from host to FPGA and then back to host involves some overhead and thus the specified bandwidth cannot be reached. However, could you kindly let us know what is the practically achievable maximum bandwidth via PCIe (v3, x16) for d5005 board (considering the overhead)? And, how to achieve it? It would be of great help to us.
You can refer to section 5. Running FPGA Diagnostics of https://www.intel.com/content/www/us/en/programmable/documentation/edj1542148561811.html#iyl1548632576241
for FPGA diagnostic sample test. The sample results might be different involving various factors of the testing environment.
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