Request of AXI bridge example for Arria 10 HPS to FPGA communication

[sunyeong]

Hi.

Our company is planning to develop new products using the Arria10 SoC.
So, I am checking the technologies needed for product development.
I need the feature for HPS to communicate with FPGA logic using an AXI bridge, but I'm having trouble finding related documentation on RocketBoard.
Looking at the TRM (Technical Reference Manual), it appears that it is accessed using Memory Map I/O.

It seems that each AXI bridge have 5 channels that consists of a number of signals. But memory offset of those signals arn't described.

I tried to find a sample application related to this function(HPS to FPGA Bridge) in GSRD, but it was not easy.

Could you please forward me any relevant examples or documents?

Regards,

Jung

[khtan]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible. 

Thank you for your understanding.

[sunyeong]

Hello, khtan.

Thank you for reply even though it is late due to system issue.

However, Our team decided to use Agilex5 instead of using Arria10.

So, I don't need answer about this issue any more.

Regards,

Jung.

[khtan]

Hi Jung,

Thanks for your information and once again I apologize for the delay in getting back to you. 

I will proceed to set this case to close-pending since the question is no longer necessary.

Thanks

Regards

Kian