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Honored Contributor I

SIIGX Dev Kit GUI clock setting

I have a Stratix-II GX Transceiver SI board, trying to use it as a 6.25 Gbps pattern generator by using one of the pre-defined test designs (gxbguictrl_top1.sof). 


I need to use an external clock source, so am using the J5 and J6 SMA connectors to input the clock. On the GUI control panel screen, under Link Control, selecting "Use SMA clock" changes the data rate on Ch. 0 from 6.25 Gbps to '40 x clk frq'. Does this mean that when using an external clock source that is under 156.25 MHz, such as mine, it's not possible to get to the full 6.25 Gbps (156.25 * 40)? Is there a way to change the number 40, especially a way to change it to something that's a power of 2? Preferably 32 or 64. 


This is all in an effort to get my scope to correctly generate an eye of the signal; the scope is incapable of using a clock divider that's not a power of 2. In this case, I'm stuck using 40. 


I have done nothing programming-wise on the actual FPGA, so I'm hoping there's an easy fix through the GUI....
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