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Altera_Forum
Honored Contributor I
737 Views

SRAM speed on Cyclone III Dev Board

Hello, 

 

does anyone has experience using the 8MB SRAM on Cyclone III Dev. Board? 

 

I'm interested in the speed of the SRAM. In the "" document on page 64 they talk about "...The Samsung part features a maximum frequency of 104 MHz (104 Mbps)...". 

So, does it mean that the SRAM can accessed with 104 Mbps or do they mean 104 Mbps per PIN. The databus has a width of 32, so is the speed 104 Mbps or 32*104=3328Mbps? 

 

Thanks for every hint!
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Altera_Forum
Honored Contributor I
30 Views

This is the clock frequency, so you multiply by 32 to get the max theoretical bandwidth. 

But be careful about two points:[list][*]the first example designs have some of the data signals mapped on the wrong pins on the FPGA. Compare the pin configurations between the schematic and the pin planner[*]the memory isn't a real SSRAM, it is a SDRAM with a SSRAM-like interface. As a result it can have a quite high latency if you don't use bursts (7 cycles at 104MHz).[/list]I wonder why Altera selected this memory on the board, it makes little sense. The main interesting aspect of an SRAM compared to a DRAM is random access time, and you don't have it here.