Stratix 10 SX dev board reset without power cycle?

[LowLevelGuy]

This may sound a bit silly,  with the Stratix 10 SX development board,   is there a way to "reboot/reset" the FPGA (so that it does its normal MSEL-based boot mode and configuration)  without power cycling it?   (I feel like I'm missing a document that would explain such)

I'm trying to work through the Secure Boot demo for Stratix 10 on the RocketBoards site.   
The design is using the "FPGA first" boot method from QSPI.  

The problem is that if I write the key to volatile virtual fuses or BBRAM,   I do not want to power cycle the board since those will be lost.

I find none of the push buttons seem to actually reset the FPGA (to where it uses the SDM to re-configures itself), including the "S3 FPGA Reset Button".

[LowLevelGuy · Accepted solution]

After reviewing the max10_system code, I found my answer and this topic can be closed.

I mistakenly thought labeled push buttons on the development board would have an actual purpose, but the published max10 logic is largely non-functional and incomplete.  

Push button reset handling, adaptive fan control, and Avalon booting  are all non-functional.  It appears to have been developed for a different board entirely.