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Stratix II GX limited sof file is not working

Altera_Forum
Honored Contributor II
913 Views

Hi, I am doing a project that uses Stratix II GX, currently, I can use the pof file from the example to run the hardware. 

The pof is loaded to the EPM570 device, I used windriver to test the hardware, everything is ok, pc can detect the device, and do read and write. 

 

However, when I try to download the limited time sof file into the FPGA, I think PC is not detecting the hardware. 

 

The live led is not flashing, which means the clk coming out of PCIE block is not initialed at all. 

 

but it's a ref design, not my own, it's from the pcie compiler 2.1 package. 

 

it passes tcl script check, timing check and modelsim simulation. 

 

Did I do something wrong? 

 

I had played various version of PCIE ref desgin, like PCIE-DMA, PCIE-DDR, they all have same problem, no working on PC. 

 

just wondering what I did wrong, did I download to the wrong device? is there any special requirement on using the limited sof file?? 

 

Hope anyone can help.
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1 Reply
Altera_Forum
Honored Contributor II
115 Views

When you upload a time limited .sof file, Quartus will then open a window saying that it is running in evaluation mode. Do you close this window? If yes, the design in the FPGA will stop working.

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