Stratix IV GX Pin Assignment

[Altera_Forum]

Hi, 

 I'm working on the Stratix IV GX 230 board and I'm trying to use the Triple Speed Ethernet in RGMII mode with MDIO. I did everything well untill the moment I needed the PIN in order to connect the MAC with the PHY. But I couldn't find any information concerning the following pin: For the MDIO: -mdio_oen -mdio_in -mdio_out -mdc  For the RGMII: -tx_control_to_the_triple_speed_ethernet_0 -rx_controle_from_the_triple_speed_ethernet_0 -tx_clk_from_the_triple_speed_ethernet_0 -rx_clk_from_the_triple_speed_ethernet_0 -rgmii_in_from_the_triple_speed_ethernet_0 -rgmii_out_to_the_triple_speed_ethernet_0  All I could find was the PHY PIN assignment for the SGMII with LVDS transceiver there: http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf  And even the documentation about the bank of IO couldn't tell more about that.  Have anyone ever managed to use the RGMII with the Stratix IV in order to have an Ethernet output?  Thank you.  Michel

[Altera_Forum]

I was also thinking that the signal I could see was because of a delay instead of an answer coming from the PHY. 

 I also added the enet_resetn since it wasn't there before and I linked it to the PIN V31 as indicated in the documentation. And I forced it to my the same level as my global resetn signal.  I'm actually trying to debug my software but everytime I have a breakpoint before seing the message: ERROR : PHY[0.0] - No PHY connected! I don't go in the alt_tse_mac_get_phy() function and I don't even have the altera_avalon_tse.c file in my project, all I have is the altera_avalon_tse.o or altera_avalon_tse.d   I'll try to find the answer but the debuger has never stepped into the altera_avalon_tse.c file even though it could print and execute the alt_tse_mac_get_phy() function. Should I add this file to my project?  I'll tell you if the enet_resetn changes anything. (I also put probe on it)

[Altera_Forum]

I have checked that my enet_resetn is always at 1 when the MDIO is trying to establish a connection with the PHY. 

 I'm still trying to debug the software.

[Altera_Forum]

The altera_avalon_tse.c should be in the bsp. 

As another way to debug, you can add printfs to the function, As an example print out what you get for id1 and id2 on each of the 32 PHY addresses.

[Altera_Forum]

I have already tried to printf the id1 and the id2 when the software tries the 32 PHY addresses and everytime it does, I have phyid1 = phyid2 = 0xFFFF. 

 And I don't have any bsp since I'm using Nios II IDE instead of eclipse nios 2. But when I modify the altera_avalon_tse.c code I have new printf() notifications.  Is it normal that the phyid doesn't even changes while the Phyaddr value changes?

[Altera_Forum]

0xFFFF means either that the PHY isn't answering or that the TSE doesn't get it. 

You should have a different set of values on one of the PHY addresses. Is there any reference with an Ethernet interface delivered with the kit? Is the PHY working? I mean at the other end of the Ethernet cable, does the device you connect say that the link is active?

[Altera_Forum]

I think that the PHY isn't responding since I don't get any real value on the Signaltap. So do I have to change anything with the MDIO or MDC or should I focus on the initialization software? (I tried to debug the software but it seems that the PHY won't answer) 

 There are reference design with ethernet interface on it that I've tried and it actually worked on the board, I guess it's just me who can't make it work with my project even though I do exactly the same thing as what is indicated in the reference design.  In the other end of the cable, I have a computer that doesn't get any data when I have a WireShark active. I guess that's because my PHY isn't working yet.  I guess my TSE work since my MAC is detected when I use the Simple_socket_server.  It's just the MDIO that can't establish the correct configuration with the PHY in the SSS software or maybe that my MDIO bus isn't synthetized as a tristated bus maybe?  Thank you for all your help Daixiwen.

[Altera_Forum]

Could you have a look at the RTL viewer on the MDIO/MDC pins and see if it is synthesized correctly? If possible compare with the reference design and check if you can spot any difference. 

The fact that it works with the reference design proves that the hardware is working, so trying to spot a difference between the reference design and your project should help you find what's wrong. You could also add a signaltap probe on the reference project and see if you can spot an answer from the PHY.

[Altera_Forum]

Sorry for the very late answer I haven't been working on FPGA for a while. 

I actually managed to establish a connection with the Triple Speed Ethernet by starting from scratch and everything went fine.  Thank you for your help Daixiwen.