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Timing Constraints for SPI Master

Annu
Beginner
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I have a system clock which is at 26 MHz (CLK A). It is used to generate the ADC SPI Clock which is of 13 MHz (CLK B)being  generated from the CLKA at certain states of  a state machine. Else CLK B is always held low. what are the necessary constraints required for this clock and it also affects some other registers in the system

 

 

 

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ShengN_Intel
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