I'm currently using the app_msi_req interface to generate MSI interrupts on the host.
Should I be using that interface if I'm implementing an Avalon-MM endpoint or should I be using the rxm_irq interface? I ask because I do see my host-driver's interrupt handler called, but it gets call a total of 12 times for a single interrupt pulse. The clock running the state-machine logic that drives the request signal high is 125 MHz, which is the same rate as the PCIe core clock. Why am I seeing these extra calls to the interrupt handler?
I figured out now that I should be using the rxm_irq lines to drive interrupts from my MM master through the PCIe core to the PCIe interface. Now, I just need to know the rxm_irq line's signal timing. Should I pulse it and trust the PCIe core to handle send and ack protocol with the root complex or do I need to implement some logic that will clear the interrupt through the CRA slave interface?