FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6020 Discussions

Transceiver Receiver PLL Problem

Honored Contributor II

i have one of these arria v development boards.i'm using transceiver native megafunction. my transceiver's receiver CDR PLL tries to capture the incoming signal and extract clock from it, but time after time it looses the track... i mean if you would look at signal tap's rx_std_clkout it works correctly and at some point bam... silence. for ~1us . and then it comes back to extraction again. if i force CDR to lock to reference clock only (not datastream) rx_std_clk works perfectly.... it seems that either receiver buffer is not configured correctly or something... i know that my internal reference clk and datastream's clk slip in phase all the time. and it seems like when both clocks are in some particular phase, CDR PLL looses the track.... and as the phase continues to slip, CDR catches up again. i don't know... it's my assumption. 


i tried to see this extracted clock on the oscilloscope but could not locate the silent dead spaces inside it... however i clearly see the silent spaces on signal tap window. 


it also may be the " offset cancellation" issue. but i do have Transceiver Reconfiguration Controller and it's reconfig_busy is asserted low. meaning offset cancellation control logic IP within the Transceiver Reconfiguration Controller has ended it's job successfully. rx_lockedtodata output pin from the megafunction is constantly high, indicating lock has been achieved. 


what else may be causing such error???
0 Kudos
0 Replies