Unable to detect 100Hz input signal properly

[Harsha4]

Hi,

We are using cyclone10lp in one of our design.

In that design, we are trying to take a 100Hz clock input and use it for some application but as soon as it enters FPGA the signal is getting random intermediate logic highs and lows. Able to observe these random level changes in signal tap as well.

100Hz signal is connected to DIFFIO_R45P pin.

Input signal is clean and no such spikes are present in the clock.

My main input clock is 25MHz and it is given to CLKUSR pin.

As an experiment, have tried to take this 100Hz clock in and assign to a different pin as output and see the wave through CRO, i am seeing many voltage spikes during transition of 100Hz clock from high to low or low to high. 

Note sure why FPGA is unable to detect this 100Hz clock properly, please suggest what i can do to detect the 100Hz input clock properly.

Thanks & Regards,

Harsha.

[FvM]

Hi,
sounds like the 100 Hz signal has low dV/dt (slow edges), in this case seeing multiple transitions per edge is just expectable. FPGA requires digital signals with fast edges, e.g.  < 1 ns tr/tf if edges matter. Did you try to enable schmitt-trigger for the respective input? 

Regards
Frank

[FvM]

Hi,
I was under the assumption that Schmitt-Trigger function is supported with Cyclone 10 LP for all I/Os, but that's only the case for MAX 10 FPGA series.

Possible options for Cyclone 10 LP are
- external Schmitt-Trigger 
- digital debounce logic, suppressing succeeding edges for a certain time period after first rising or falling edge
- implement the 100 Hz input as bidirectional inout pin with disabled output and enable bus-hold feature, can work as Schmitt-Trigger emulation in combination with source impedance.  

[AqidAyman_Intel]

Hi Harsha,

Any updates you want to share with us? Have you tried the suggestion from Frank?

Regards,

Aqid