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Altera_Forum
Honored Contributor I
958 Views

Using SSRAM on cycolne III board

Hi, 

 

I am fresher & new to this FPGA platform. 

 

Flash & SSRAM share data & address lines. 

For SSRAM the address range used is 19 downto 2. 

 

The SSRAM mounted in board is IS61LP25636A-200TQLI,but in SOPC builder,it is cypress CY7C1380C SSRAM.i used the same available cypress ssram & gave size as 1Mbyte(size of mounted ssram). 

I am not sure about giving latency (2 or 3 are available in drop down list) 

 

The base address of this SSRAM in SOPC is 0x01100000.& I used folowing C program in NIOS II to write & read starting 10 locations of SSRAM. 

 

unsigned int SRAM_memory_check() 

unsigned int sram_mem_reg=0xffff; 

unsigned int sram_i=0; 

unsigned int sram_offset; 

unsigned int sram_data=0; 

 

 

for (sram_i=0;sram_i<9;sram_i++) 

 

 

sram_offset=0x00000000+4*sram_i;  

sram_data=0x00000001+sram_data; 

 

printf("sram_data_written_at_location(%d)is :0x%8.8x\n",sram_i,sram_data); 

IOWR_32DIRECT(0x01100000,sram_offset,sram_data); 

 

sram_mem_reg=IORD_32DIRECT(0x01100000,sram_offset); 

 

printf("sram_register_(%d): 0x%8.8x\n",sram_i,sram_mem_reg); 

 

 

return 0; 

 

The above program is called in main.c 

 

The above program is resulting in a constant read of 0x00001080 in all locations. 

 

Please help me out in this ASAP. 

Thanks in Advance.
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3 Replies
Altera_Forum
Honored Contributor I
31 Views

How about write and read 0x00 to the 10 locations before entering the for loop ? This is to make sure you are not reading some uninitialized values of the SRAM.

Altera_Forum
Honored Contributor I
31 Views

No,it is as good as replacing sram_data wtih 0x00, in the above IOWR or IORD functions,right. 

i tried it,still it is giving out 0x00001080 in all locations. 

 

Moreover,I used the memtest.c template given in the examples folder in the installation directory. 

ddr sdram memory test is passed,but test is not passed for ssram. 

There is something wrong.Here,since the address,data lines are shared, & i have given reset memory vector as flash.will it cause any problem? 

I will try giving both reset & exception vectors of nios cpu as onchip memory.Let us see.
Altera_Forum
Honored Contributor I
31 Views

Hi Leen, 

 

It is a silly mistake from side.I had forgotten to put clock output of pll(clk of ssram) in the port section of entity of top level vhdl code.Hence had not assigned the pin for ssram clock. 

 

now,the problem is solved.I am able to write into & read from SSRAM. 

 

Regards, 

Raghavendra.S