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stratixIII_3sl150_dev development kit layout

Honored Contributor II

hello all 


I have to design a new board based in the stratixIII_3sl150_dev development kit. 


I checked the layout of the developement board and I do not understand why the "Ddr2_Dimm_Dqxx" nets in layer 4 are 5.25 mils width and in the other layers are 5.75 mils 


the differential pairs are 4 mils which it´s ok. 


thanks in advance
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2 Replies
Honored Contributor II

Maybe because impedance modeling showed the required width?

Honored Contributor II

normally should be like that, but in this case stackup it is simetrical and the same group of nets have different width. this means that same group of nets have different impedance which it is not possible.  


I checked the board and it is working fine so the layout it is ok so I´m wrong, or the docs are wrong. 


if somebody can give some of light I will apreciate. 


btw I´ve checked the rev C, and I have not rev B nor rev A 



happy new year for everybody