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AJung123
New Contributor I
642 Views

Using devmem2 to write to a register hangs the Stratix 10

Hello,

 

I am using the Stratix 10 and have devmem2 included in the Yocto build. I slightly modified the GSRD with a different sysID and included two msgDMAs (one is MM-Streaming and the other is Streaming-MM, both are connected to the HPS) and a single clock FIFO (sits in between the two DMAs). I was able to read the sysID using devmem2 but when writing to the control register of either msgDMA, the board hangs. Any ideas on what is going wrong?

 

 

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11 Replies
Fawaz_J_Intel
Employee
259 Views

Hello Alexander,

It is not easy to define the root cause of such a behavior. I had the same issue before with memtool, trying to access an address from FPGA side, and the system was hanging. After long time of debugging, I noticed that there was addressing mismatch that caused this behavior.

 

The only way to know what is going on is to add a signaltap file and see if the mSGDMA is responding. Furthermore, double check the connection of this IP, there might be something missing.

 

Thanks

AJung123
New Contributor I
259 Views

Hello,

 

I have received your email and replied with the qsys attached. I will also attach it here for reference.

Fawaz_J_Intel
Employee
259 Views

Hello sir,

I have checked your Qsys file.

Connection wise, everything seems fine. Since you are not able to access the control port of the msgdma, I would suggest to debug the system using SignalTap to see where is the breakpoint that causes the system to hang.

Alternatively, you can add Nios II processor and try to access the msgdma as well, if you are able to read the control port via Nios II, this means there might be an issue with the addresses you are using with devmem2.

 

thanks

AJung123
New Contributor I
259 Views

Ok, thanks for your reply. Hypothetically, if I can get this to work, I should be control the msgDMA with devmem2 and writing the appropriate values into the ports available correct?

Fawaz_J_Intel
Employee
259 Views

Hello sir,

Yes, you can read from the control/status port of any IP on FPGA from HPS side. The first read is important to make sure the bridge is working and no issue exists.

Once you are able to communicate to this IP, you can initialize the IP and configure it based on the software flow of the mSGDMA. However, this way of bare-metal development might be hard to achieve from application point of view.

My recommendation is to use the mSGDMA linux driver to make the application development simpler.

https://github.com/torvalds/linux/blob/master/drivers/dma/altera-msgdma.c

 

thank you,

AJung123
New Contributor I
259 Views

Hello,

 

So I was able to read and write to the msgDMA and was successful in controlling it through the use of devmem2. However, I'm not entirely sure how to use the linux driver/how to include it as part of my yocto build, etc. Any explanations would be great. Thanks

Fawaz_J_Intel
Employee
259 Views

Hello,

you need to generate a newer copy of the device tree of your system. It will include the mSGDMA information that will help the kernel to load the compatible driver.

To enable this driver in the kernel, you need to modify the kernel through menuconfig command.

 

thanks

AJung123
New Contributor I
259 Views

Would you happen to know what should the new device tree look like/how to add the mSGDMA to the device tree? I haven't seen any articles showcasing how to add it to the device tree and similarly to this post: https://forum.rocketboards.org/t/ip-msgdma-linux-driver/1919, I am struggling with the same things. I also am unsure as to how to enable the driver in the kernel. I am still relatively new to this so any more guidance would be great.

Fawaz_J_Intel
Employee
259 Views

Hello,

from this link:

https://rocketboards.org/foswiki/Main/GettingStarted

 

You can get all the information needed for building Linux on HPS. You need to select your device, then the Quartus version, and finally select the step you want to learn about it. Device tree generation is on of these steps.

 

thank you.

 

AJung123
New Contributor I
259 Views

Hello,

 

I am working with Quartus v19.1 . I see the step on crafting the tree manually in "Step 7 - Compile Linux for Stratix 10." It says "Add this piece of dtsi fragment as #include "socfpga_stratix10_ghrd.dtsi" in the file socfpga_stratix10_socdk.dts. Compile it in the kernel along with socfpga_stratix10.dtsi during kernel compilation." I am having trouble understanding this step and was wondering if I could get some clarification?

Fawaz_J_Intel
Employee
259 Views

Hello sir,

This might be another case which is different from the current thread. Generally, this inclusion is for device tree preparation while bitbake is compiling your embedded linux system, it will compile the device tree for you with the FPGA related peripherals.

 

Feel free to open another thread if you still have inquires on Linux compilation.

 

thank you

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