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Verilog code of sample decimation on DE1 SoC.

qizilbash
Beginner
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Can someone help me with the code of sample decimation on the audio signal of DE1 SoC?

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SyafieqS
Employee
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Attached is a small design example of a simple Verilog module that performs decimation by a factor of 2. This means it takes every other input sample and discards the rest. This is a basic example of decimation by a factor of 2. You might need to adjust the bit widths, decimation factor, and other aspects of the module. Also, you prolly want to include additional logic for handling synchronization and other functionalities based on your application needs.

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SyafieqS
Employee
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Please take a look at it design attached. For better optimization with hardware and development, I suggest to use FIR II Intel® FPGA IP Core.

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/dsp/fir-compiler.html


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SyafieqS
Employee
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Let me know if there is any update from previous reply


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SyafieqS
Employee
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey


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qizilbash
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