Which is the preferred way to configure FPGA in Cyclone V SoC?

[Ozzuu]

We have a Cyclone V SoC on a custom board in a satellite. Our only access to FPGA is via HPS. We aim to run experiments on this FPGA and strictly check that the experiments fulfill certain conditions like matching pin configuration and bridge configuration etc. We are able to configure the FPGA with a new design using following methods,

1 ) By modifying Uboot environment to point to our new design and performing a reset.

2)  From Linux (running on HPS) using device tree overlay and then enabling H2F and H2FLW bridges using a custom tool to write to brgmodrst register from Linux.

My questions are,

1) Is there a preferred way out of these two? and why?

2) To be specific does configuring FPGA from Linux has any specific disadvantages? We prefer configuration from Linux, in order to not play with Uboot environment.

3) Is enabling/disabling bridges by writing to brgmodrst from Linux perfectly normal?

We are aware that enabling FPGA 2 SDRAM bridge from Linux neither possible nor recommended and we are not attempting that.

[EBERLAZARE_I_Intel]

Hi,

1) Is there a preferred way out of these two? and why?

In our design example mostly the FPGA is configured during Uboot, but other methods works as well.

2) To be specific does configuring FPGA from Linux has any specific disadvantages? We prefer configuration from Linux, in order to not play with Uboot environment.

This depends on customer design and usage, sometime users want to have access to SDRAM and other FPGA IO or features that they have used in their design that is needed in early phases.

3) Is enabling/disabling bridges by writing to brgmodrst from Linux perfectly normal?

Typically, bridge is enable in Uboot environment, using the Uboot script "run bridge_enable_handoff".

I hope this answers all your questions.