Why my design is not generated when using the third EMAC on Arria 10 SoC?

[AJuba]

Hello ,

We have designed a custom board which has some industrial Ethernet testing.

When enabling three EMACS, the third EMAC (2) gives a warning message of invalid clock settings.

Is it a known issue? anyone can help?

Thanks

[AJuba]

Anyone can help me on this?

[FawazJ_Altera · Accepted solution]

Hello AJuba,

This is due to a bug within Platform Designer (previously Qsys). There will be a patch release in 18.1.1

Until the time of the release, you will not be able to use 3 EMACs on Arria 10.

Thanks

[AJuba]

Thanks FJumaah for your reply.

Now it make sense.

I will wait for 18.1.1.