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AJuba
Beginner
958 Views

Why my design is not generated when using the third EMAC on Arria 10 SoC?

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Hello ,

We have designed a custom board which has some industrial Ethernet testing.

When enabling three EMACS, the third EMAC (2) gives a warning message of invalid clock settings.

Is it a known issue? anyone can help?

 

Thanks

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1 Solution
Fawaz_J_Intel
Employee
81 Views

Hello AJuba,

This is due to a bug within Platform Designer (previously Qsys). There will be a patch release in 18.1.1

Until the time of the release, you will not be able to use 3 EMACs on Arria 10.

 

Thanks

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3 Replies
AJuba
Beginner
81 Views

Anyone can help me on this?

Fawaz_J_Intel
Employee
82 Views

Hello AJuba,

This is due to a bug within Platform Designer (previously Qsys). There will be a patch release in 18.1.1

Until the time of the release, you will not be able to use 3 EMACs on Arria 10.

 

Thanks

View solution in original post

AJuba
Beginner
81 Views

Thanks FJumaah for your reply.

Now it make sense.

I will wait for 18.1.1.

 

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