FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Worst-case operating conditions

ymiler
Employee
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The timing analysis is performed to check for violation with the fastest speed grade "type" of FPGA defined in the project and with the slowest for the upper and lower temperature limit

 

I would like to ask if there is a option to define my  worst cases (temp & voltage)

 

Thanks

 

Yishay

 

 

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sstrell
Honored Contributor III
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No.  The operating conditions/timing models are specific to the device you are targeting.  When you manually generate the timing netlist, you can select a different speed grade of the same device, but other than that, the models to use are baked into the timing analyzer.

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ymiler
Employee
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