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Beginner
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Writing to SDRAM from FPGA (DE0-Nano-SoC board)

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Hi,

 

I have designed a hardware component in VHDL that generates 32-bit data at a rate of 1 MHz. The generated data has to be stored in the SDRAM so that I can read it from the HPS. The problem is that I don't know how to sent it. From what I have read (and think I understand), there are two ways to do this:

 

  1. Use an External Bus to Avalon Bridge to send the data to the L3 switch and then to the SDRAM.
  2. Use a SDRAM controller and send the data directly to the SDRAM.

 

Do you recommend any of these options or should I try another one. I have some experience in microcontrollers and FPGAs but not in SoCs so any advice would be appreciated.

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Employee
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Hello, It depends on the data size. I recommend to use DMA controller and send the data through address span extender to HPS SDRAM, so that HPS can read it. The other approach would be, connecting the H2F bridge to SDRAM controller of FPGA, and read through it. Please let me know if you need further assistance, I have done some data transfer between FPGA and HPS on DE10 nano, which is almost similar to DE0 Nano SoC. Thanks

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Employee
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Hello, It depends on the data size. I recommend to use DMA controller and send the data through address span extender to HPS SDRAM, so that HPS can read it. The other approach would be, connecting the H2F bridge to SDRAM controller of FPGA, and read through it. Please let me know if you need further assistance, I have done some data transfer between FPGA and HPS on DE10 nano, which is almost similar to DE0 Nano SoC. Thanks

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Beginner
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Hello FJumaah,

 

I thought the FPGA could write directly into the SDRAM Controller as a master. Is there any reason why I should use the DMA? Also, I am beginning to doubt using the SDRAM is the best option for my project. I provide more details below.

 

DETAILS

I have designed an IP core that receives 4 consecutive bytes and concatenates them into a 32-bit word (basically a demux). I need to send the word somewhere so that the processor (running Linux) can pack the data and send it through Ethernet in UDP frames.

 

Yesterday, I read in other forum that one way to implement something similar is to use an On-Chip RAM with two slave ports (FPGA writes to RAM while HPS reads). Do you think that could work?

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Employee
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Hello sir, The DMA will help to offload the data transfer task from Nios II (or any FSM). Its up to you if you want to use it or not. Choosing SDRAM or OCRAM depends on the data size that you want to hold on FPGA before sending it to HPS. OCRAM can be helpful since the latency is much lower than the SDRAM. from HPS side, you can access both as long as the Qsys connections are correct. Thanks
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Employee
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Hello, I would like to know if you still have inquires related to this thread. Thanks
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Beginner
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Hi,

 

I am still in the process of implementing the system using an On-Chip RAM. I will probably have more questions in the future. In the meantime, thank you very much for the advice.

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