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Hi sir,
I am facing one strange problem, details as follows:
1. when I use gxp_dedicated_clock for the reference clock of the transceiver fpll, after power-on, cal_busy signal is low, but the locked signal is not asserted infinitly, I am sure the clock is clean and stable; (Transceive in cascading mode, and the problem at the upstream fpll, i think the problem exists at the downstream fpll yet).
Note: when power-on, the reference clock is not my need, firstly, I adjust the clock of the reference clock, then I asserted pll_powedown long time, and the fpll can not work normally;
2. Based 1, I make the fpll work under core mode, and provide the same reference clock, and do the same thing as 1's note, and the fpll can not work normally. When I asserted the pll_powerdown, the fpll can not lock and output the error frequency.
3. after 2, I change the reference clock to lvds io(clk pins), and do the same thing as 2, when I power on, I found the fpll can output correct frequency, and fpll can lock; but when I assert the pll_powerdown and not release, I find the fpll can output correct frequency, and fpll locks stilly; That means, pll can work at reset state, and pll_powerdown has no effect.
soft:: quartus 16.0
develope board: a10gx_si_e4 (10gx115s2f45i1sg)
example:
altclk_ctrl inst_0(.inclk(clk_i), outclk(ref_clk));
fpll_test fpll_test_inst(.outclk0 (outclk), .pll_cal_busy(cal_busy), .pll_locked(clk_locked),pll_powerdown(pll_powerdown), .pll_refclk0(ref_clk));
Could some help me about this problem, thanks.
Best regards,
Lambert
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HI,
There is known bug on pll_powerdown signal. You can checkout below KDB link
Thanks.
Regards,
dlim
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HI,
There is known bug on pll_powerdown signal. You can checkout below KDB link
Thanks.
Regards,
dlim
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