arria 10 interoperability reference design is not work..!

[Altera_Forum]

Hello, 

I'm a beginner in FPGA. I'm going to learn the FPGA this year.  I want to make a DRFM(Digital Radio Frequency Memory).  I follow the document(http://www.alterawiki.com/uploads/3/3c/a10_jesd204b_ad9144_ad9625_ug.pdf)  I prepared blow - Arria 10 Development kit - AD9625 EVM, AD 9135 FMC  - Windows 7@64bit, 8G RAM, Quartus II 17.0(standard ed.)  But example is not working.  system log(attached) CONF_DONE pin failed to go high in device 1 . Make use all communication cables are securely connected, ....  According to the log, I have changed the device 10AX115S2F45ISG(dev kit.)  And then, Start Compilation.. Some errors has occured. ----------------------------------------------------------------------------------------- In fitter(Place & Route) Error# 18757, physical synthesis has been replaced by spectra-q physical synthesis for this device family..  <jesd_204b_ed.qsf> I have modified it. from  set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON to comment (#).  And re-compilation error occured in EDA Netlist Writer 204012 Can't generate netlist output files because the file... 204009 Can't generate netlist output files because the license for encrypted file... -----------------------------------------------------------------------------------------  The compilation is done. And the output_files is generated. But this is irrelevant. The original in master_file is <jesd_204b_ed.sof> but generated file in output_file is <jesd_204b_ed_time_limited.sof>  Anyway, I run the programmer and download it. But it not working. How can I do? --------------------------------------------------------------------------------------------------------------------------------------------- solved.. I had change the Q-sys files.

[Altera_Forum]

In NIOS II software builder tools 

 Comment this.(main.c) 77// if (ResetForce(link, XCVR_LINK_FRAME_RESET_MASK, HOLD_RESET_MASK, held_resets) != 0) 78// return 1;  p.s. Don't forget change parameter in main.h.  Have a nice day!

[johnzaf]

Dear all,

Has this design worked on this device (10AX115S2F45ISG, production device)? I tried with all versions of quartus 15.1 to 19.1 pro but it does not work. I have tried with the dacs ad9144 and 9154 too.

On 15.1 no sof is created because quartus says that the device is "advanced". On 16.1 the sof is created but I can't download the .sof on board because of the opencore license management. I download the .sof but jtag loses connection immediately.On 17 and forwards I can download the design but no data comes out of the DAC. 

I observed when I run the software that the SPI seems to work and all plls are locked but it says that TX calibration has failed and then when it reads the jesd204 configurations from the dac, all the parameters are zero.

I followed the steps from this guide https://www.intel.com/content/dam/altera-www/global/en_US/uploads/3/3c/A10_jesd204b_ad9144_ad9625_ug.pdf

Any ideas?

Thanks in advance.

[johnzaf]

Hi all,

Did anyone managed to run the 'Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design' on the '10AX115S2F45ISG' device?

Thank you