I am trying to pass a clock to a differential sma output(pins c42,c41) on my board (Arria 10 GX Development kit).
But the fitter shows me this error:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic pin in region (0, 143) to (0, 143), to which it is constrained, because there are no valid locations in the region for logic of this type.
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Please provide more details on the design:
1) What is the IO standard applied to these pins?
2) Is the XCVR bank correctly clocked?
3) What are the other pins located in this bank?
Note that these pins are transceiver output only pins and cannot be used as a normal GPIO (reference: device pin-out file).
If you can provide a simple design to reproduce this case, we can debug it further.
Hi thanks for the reply,
I just want to take a clock out of these differentials sma. I am trying with a simple design now and I try to connect for example the 50mhz clock (pin au33) to these sma.
1) the pin planner allows me to choose the 'high speed differential I/0' only for these pins (c42,c41)
2) how to check this?
3) i dont use other pins. I just want to connect pin au33 for example to these pins (c42,c41). Is this possible? Is any other way to connect a clock to these pins ?
C42 and C41 are transceiver pins and their data rate is limited as per datasheet. Minimum =1 Gbps.
As your requirement is 50 MHz around, I am afraid you can do that.
Thank you Sir,
I managed to find this out.
I wonder now if it's possible to customize the 'data pattern generator IP' that it is connected with the 'Transceiver native PHY IP' (in an example design) in order to send pulses at lower data rate (by sending lots of '1' and '0' in a row) or if I could create my own IP that does that. Would you recommend such thing ?
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