FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5203 Discussions

difficulty regarding signal tap analysis

Altera_Forum
Honored Contributor II
970 Views

I do not know to use signal tap analysis simulink altera blockset which is used for dsp application. 

can you please help me to use it.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
243 Views

Please clarify what you're trying to do. I could recap all the documentation on SignalTap, but imagine you're asking for something more specific(and I'm assuming you've already looked through the website and documentation on SignalTap). Note that most SignalTap users use it as a back-end tool for debugging. That means they don't put it in their design files, whether they be schematics, HDL, or Simulink files. They instead use at it as a design file(.stp) in Quartus that pulls signals from an already synthesized, and often already placed and routed, design. That being said, you may want to use it in your Simulink file in a manner similar to a scope, just in hardware rather than simulation. (I haven't done that myself, but am sure someone else can add their experience.) Anyway, could you elaborate more on what you're trying to do and what you've already tried(i.e. where you're getting stuck).

Reply