FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.
5841 Discussions

difficulty regarding signal tap analysis

Altera_Forum
Honored Contributor II
1,330 Views

I do not know to use signal tap analysis simulink altera blockset which is used for dsp application. 

can you please help me to use it.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
603 Views

Please clarify what you're trying to do. I could recap all the documentation on SignalTap, but imagine you're asking for something more specific(and I'm assuming you've already looked through the website and documentation on SignalTap). Note that most SignalTap users use it as a back-end tool for debugging. That means they don't put it in their design files, whether they be schematics, HDL, or Simulink files. They instead use at it as a design file(.stp) in Quartus that pulls signals from an already synthesized, and often already placed and routed, design. That being said, you may want to use it in your Simulink file in a manner similar to a scope, just in hardware rather than simulation. (I haven't done that myself, but am sure someone else can add their experience.) Anyway, could you elaborate more on what you're trying to do and what you've already tried(i.e. where you're getting stuck).

0 Kudos
Reply