Hi! Can someone please post or share the Altera Max10 JTAG secure unlock example design described in the user guide for the Max10?
This link does not work based on previous post: https://fpgacloud.intel.com/old_design_store/platform/15.0.0/Standard/max10-jtag-secure-unlock/
I understand that the example design is old and only runs on the old Quartus tool BUT the example will show how to unlock the FPGA after it has been locked. I also understand it uses the JTAG WYSIWYG atom fiftyfivenm_jtag but only the top level component declaration is shown in fiftyfivenm_components.vhd.
If anyone in the community has this example code design, please let me know.
Thank you!
