the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

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the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

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Hello everyone,

I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the output of one external PLL to drive them, but it always was fittered failure, I read the clock , PLL and I/0 part of Arria V datasheet, it can't say that the same external PLL can not drive lvds pairs in different BANK obviously. I want to know what kind of routing resources (GCLK, RCLK or PCLK) the arriav_pll_lvds_output of the PLL chooses.

Can you give me some help?

Thank,

Lambert

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