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trace length of the PCIe

dsun01
New Contributor III
417 Views

Dear Experts, 

I am studying the PCIe of the Arria 10 SoC EVM board,  the PCIe slot is defined for a root. I am going to use a crossover cable to connect it to a PC, and use it as a end point.  I noticed that PCIe lanes is not required matching the length. How about the reference clock. I need make minor modification of the reference clock on the board(from driver to receiver). so I can direct the reference clock from the PC to the FPGA on board. that will change the trace of the length.  is there any requirement to the reference clock in length reference to the lanes.  what is the timing requirement to the reference besides the 100Mhz frequency.

 

Thanks

David

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1 Solution
KhaiChein_Y_Intel
399 Views

Hi David,


The Intel Arria 10 Hard IP for PCI Express supports for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported. For SRNS, you have to make sure that the worst case is 600 ppm.


Thanks

Best regards,

KhaiY


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2 Replies
KhaiChein_Y_Intel
400 Views

Hi David,


The Intel Arria 10 Hard IP for PCI Express supports for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported. For SRNS, you have to make sure that the worst case is 600 ppm.


Thanks

Best regards,

KhaiY


KhaiChein_Y_Intel
383 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


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